Identificacion Principal del registro INGC-EBK-000086

Control Number Identifier AR-LpUFI

LAST MODIFICATION DATE 20160826101449

CONTROL FIELD cr nn 008mamaa

CONTROL FIELD 130805s2014 xxu| s |||| 0|eng d

a International Standard Book Number 9781461473244

a Standard number or code 10.1007/978-1-4614-7324-4

a Personal name Mehta, Ashok B.

a Title SystemVerilog Assertions and Functional Coverage

h Medium [libro electrónico] : ;

b Remainder of title Guide to Language, Methodology and Applications /

c Statement of responsibility, etc by Ashok B. Mehta.

a Place of publication, distribution, etc New York, NY :

b Name of publisher, distributor, etc Springer New York :

b Name of publisher, distributor, etc Imprint: Springer,

c Date of publication, distribution, etc 2014.

a Extent xxxiii, 356 p. :

a Formatted contents note Introduction -- System Verilog Assertions -- Immediate Assertions -- Concurrent Assertions â_" Basics (sequence, property, assert).- Sampled Value Functions   $rose, $fell -- Operators -- System Functions and Tasks -- Multiple clocks -- Local Variables -- Recursive property -- Detecting and using endpoint of a sequence -- â_~expectâ_T -- â_~assumeâ_T and formal (static functional) verification -- Other important topics -- Asynchronous Assertions !!! -- IEEE-1800â_"2009 Features -- SystemVerilog Assertions LABs -- System Verilog Assertions â_" LAB Answers -- Functional Coverage -- Performance Implications of coverage methodology -- Coverage Options (Reference material).

a Summary, etc This book provides a hands-on, application-oriented guide to the language and methodology of both SystemVerilog Assertions and SytemVerilog Functional Coverage.  Readers will benefit from the step-by-step approach to functional hardware verification, which will enable them to uncover hidden and hard to find bugs, point directly to the source of the bug, provide for a clean and easy way to model complex timing checks and objectively answer the question â_~have we functionally verified everythingâ_T.  Written by a professional end-user of both SystemVerilog Assertions and SystemVerilog Functional Coverage, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects.  Readers will be empowered to tackle the modeling of complex checkers for functional verification, thereby reducing drastically their time to design and debug.   ·         Covers both SystemVerilog Assertions and SytemVerilog Functional Coverage language and methodologies; ·         Provides practical examples of the what, how and why of Assertion Based Verification and Functional Coverage methodologies; ·         Explains each concept in an easy to understand, step-by-step fashion and applies it to a real example; ·         Includes practical labs that enable readers to put in practice the concepts explained in the book.

a Topical term or geographic name as entry element Engineering.

a Topical term or geographic name as entry element Microprocessors.

a Topical term or geographic name as entry element Electronics.

a Topical term or geographic name as entry element Microelectronics.

a Topical term or geographic name as entry element Electronic circuits.

a Topical term or geographic name as entry element Circuits and Systems.

a Topical term or geographic name as entry element Instrumentation.

a Topical term or geographic name as entry element Processor Architectures.

u Uniform Resource Identifier (R) http://dx.doi.org/10.1007/978-1-4614-7324-4

c item type EBK

a descripción COM