001 -Identificacion Principal del registro
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Identificacion Principal del registro
INGC-EBK-000140
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003 -Control Number Identifier
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Control Number Identifier
AR-LpUFI
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005 -LAST MODIFICATION DATE
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LAST MODIFICATION DATE
20160907095451
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007 -CONTROL FIELD
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CONTROL FIELD
cr nn 008mamaa
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008 -CONTROL FIELD
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CONTROL FIELD
131113s2014 xxu| s |||| 0|eng d
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020 -INTERNATIONAL STANDARD BOOK NUMBER
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a
International Standard Book Number
9781461494058
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024 -OTHER STANDARD IDENTIFIER
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a
Standard number or code
10.1007/978-1-4614-9405-8
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100 -MAIN ENTRY--PERSONAL NAME
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a
Personal name
Mandal, Ayan.
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245 -TITLE STATEMENT
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a
Title
Source-Synchronous Networks-On-Chip
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h
Medium
[libro electrónico] : ;
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b
Remainder of title
Circuit and Architectural Interconnect Modeling /
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c
Statement of responsibility, etc
by Ayan Mandal, Sunil P. Khatri, Rabi Mahapatra.
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260 -PUBLICATION, DISTRIBUTION, ETC. (IMPRINT)
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a
Place of publication, distribution, etc
New York, NY :
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b
Name of publisher, distributor, etc
Springer New York :
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b
Name of publisher, distributor, etc
Imprint: Springer,
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c
Date of publication, distribution, etc
2014.
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300 -PHYSICAL DESCRIPTION
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a
Extent
xiii, 143 p. :
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b
Other physical details
il.
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505 -FORMATTED CONTENTS NOTE
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a
Formatted contents note
Introduction -- Clock Distribution for fast Networks-on-Chip -- Fast Network-on-Chip Design -- Fast On-Chip Data transfer using Sinusoid Signals -- Conclusion and Future Work.
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520 -SUMMARY, ETC.
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a
Summary, etc
This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.  â_¢Â Describes novel methods for high-speed network-on-chip (NoC) design; â_¢Â Enables readers to understand NoC design from both circuit and architectural levels; â_¢Â Provides circuit-level details of the NoC (including clocking, router design), along with a high-speed, resonant clocking style which is used in the NoC; â_¢Â Includes architectural simulations of the NoC, demonstrating significantly superior performance over the state-of-the-art.
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650 -SUBJECT ADDED ENTRY--TOPICAL TERM
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a
Topical term or geographic name as entry element
Engineering.
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650 -SUBJECT ADDED ENTRY--TOPICAL TERM
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a
Topical term or geographic name as entry element
Microprocessors.
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650 -SUBJECT ADDED ENTRY--TOPICAL TERM
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a
Topical term or geographic name as entry element
Electronics.
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650 -SUBJECT ADDED ENTRY--TOPICAL TERM
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a
Topical term or geographic name as entry element
Microelectronics.
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650 -SUBJECT ADDED ENTRY--TOPICAL TERM
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a
Topical term or geographic name as entry element
Electronic circuits.
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650 -SUBJECT ADDED ENTRY--TOPICAL TERM
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a
Topical term or geographic name as entry element
Circuits and Systems.
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650 -SUBJECT ADDED ENTRY--TOPICAL TERM
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a
Topical term or geographic name as entry element
Processor Architectures.
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650 -SUBJECT ADDED ENTRY--TOPICAL TERM
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a
Topical term or geographic name as entry element
Instrumentation.
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700 -ADDED ENTRY--PERSONAL NAME
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a
Personal name
Khatri, Sunil P.
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700 -ADDED ENTRY--PERSONAL NAME
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a
Personal name
Mahapatra, Rabi.
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856 -ELECTRONIC LOCATION AND ACCESS
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u
Uniform Resource Identifier (R)
http://dx.doi.org/10.1007/978-1-4614-9405-8
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942 -Biblioitem information
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929 -Medio de adquisicion
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