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Source-Synchronous Networks-On-Chip Circuit and Architectural Interconnect Modeling by Ayan Mandal, Sunil P. Khatri, Rabi Mahapatra. (Mandal, Ayan.)
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001 -Identificacion Principal del registro

Identificacion Principal del registro INGC-EBK-000140

003 -Control Number Identifier

Control Number Identifier AR-LpUFI

005 -LAST MODIFICATION DATE

LAST MODIFICATION DATE 20160907095451

007 -CONTROL FIELD

CONTROL FIELD cr nn 008mamaa

008 -CONTROL FIELD

CONTROL FIELD 131113s2014 xxu| s |||| 0|eng d

020 -INTERNATIONAL STANDARD BOOK NUMBER

a International Standard Book Number 9781461494058

024 -OTHER STANDARD IDENTIFIER

a Standard number or code 10.1007/978-1-4614-9405-8

100 -MAIN ENTRY--PERSONAL NAME

a Personal name Mandal, Ayan.

245 -TITLE STATEMENT

a Title Source-Synchronous Networks-On-Chip

h Medium [libro electrónico] : ;

b Remainder of title Circuit and Architectural Interconnect Modeling /

c Statement of responsibility, etc by Ayan Mandal, Sunil P. Khatri, Rabi Mahapatra.

260 -PUBLICATION, DISTRIBUTION, ETC. (IMPRINT)

a Place of publication, distribution, etc New York, NY :

b Name of publisher, distributor, etc Springer New York :

b Name of publisher, distributor, etc Imprint: Springer,

c Date of publication, distribution, etc 2014.

300 -PHYSICAL DESCRIPTION

a Extent xiii, 143 p. :

b Other physical details il.

505 -FORMATTED CONTENTS NOTE

a Formatted contents note Introduction -- Clock Distribution for fast Networks-on-Chip -- Fast Network-on-Chip Design -- Fast On-Chip Data transfer using Sinusoid Signals -- Conclusion and Future Work.

520 -SUMMARY, ETC.

a Summary, etc This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks.  The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized.  Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.   â_¢Â Describes novel methods for high-speed network-on-chip (NoC) design; â_¢Â Enables readers to understand NoC design from both circuit and architectural levels; â_¢Â Provides circuit-level details of the NoC (including clocking, router design), along with a high-speed, resonant clocking style which is used in the NoC; â_¢Â Includes architectural simulations of the NoC, demonstrating significantly superior performance over the state-of-the-art.

650 -SUBJECT ADDED ENTRY--TOPICAL TERM

a Topical term or geographic name as entry element Engineering.

650 -SUBJECT ADDED ENTRY--TOPICAL TERM

a Topical term or geographic name as entry element Microprocessors.

650 -SUBJECT ADDED ENTRY--TOPICAL TERM

a Topical term or geographic name as entry element Electronics.

650 -SUBJECT ADDED ENTRY--TOPICAL TERM

a Topical term or geographic name as entry element Microelectronics.

650 -SUBJECT ADDED ENTRY--TOPICAL TERM

a Topical term or geographic name as entry element Electronic circuits.

650 -SUBJECT ADDED ENTRY--TOPICAL TERM

a Topical term or geographic name as entry element Circuits and Systems.

650 -SUBJECT ADDED ENTRY--TOPICAL TERM

a Topical term or geographic name as entry element Processor Architectures.

650 -SUBJECT ADDED ENTRY--TOPICAL TERM

a Topical term or geographic name as entry element Instrumentation.

700 -ADDED ENTRY--PERSONAL NAME

a Personal name Khatri, Sunil P.

700 -ADDED ENTRY--PERSONAL NAME

a Personal name Mahapatra, Rabi.

856 -ELECTRONIC LOCATION AND ACCESS

u Uniform Resource Identifier (R) http://dx.doi.org/10.1007/978-1-4614-9405-8

942 -Biblioitem information

c item type EBK

929 -Medio de adquisicion

a descripción COM


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