Identificacion Principal del registro INGC-EBK-000205

Control Number Identifier AR-LpUFI

LAST MODIFICATION DATE 20160826112400

CONTROL FIELD cr nn 008mamaa

CONTROL FIELD 130906s2014 gw | s |||| 0|eng d

a International Standard Book Number 9783319011509

a Standard number or code 10.1007/978-3-319-01150-9

a Personal name Jamin, Olivier.

a Title Broadband Direct RF Digitization Receivers

h Medium [libro electrónico] /

c Statement of responsibility, etc by Olivier Jamin.

a Place of publication, distribution, etc Cham :

b Name of publisher, distributor, etc Springer International Publishing :

b Name of publisher, distributor, etc Imprint: Springer,

c Date of publication, distribution, etc 2014.

a Extent xvi, 162 p. :

b Other physical details il.

a Series statement Analog Circuits and Signal Processing,

x International Standard Serial Number 1872-082X ;

v Volume number/sequential designation 121

a Formatted contents note RF Receiver Architecture State-of-the-Art -- System-Level Design Framework for Direct RF Digitization Receivers -- Application to the System Design of a Multi-Channel Cable Receiver -- Realization & Measurements -- Conclusions & Perspectives.

a Summary, etc This book discusses the trade-offs involved in designing direct RF digitization receivers for the radio frequency and digital signal processing domains.  A system-level framework is developed, quantifying the relevant impairments of the signal processing chain, through a comprehensive system-level analysis.  Special focus is given to noise analysis (thermal noise, quantization noise, saturation noise, signal-dependent noise), broadband non-linear distortion analysis, including the impact of the sampling strategy (low-pass, band-pass), analysis of time-interleaved ADC channel mismatches, sampling clock purity and digital channel selection. The system-level framework described is applied to the design of a cable multi-channel RF direct digitization receiver. An optimum RF signal conditioning, and some algorithms (automatic gain control loop, RF front-end amplitude equalization control loop) are used to relax the requirements of a 2.7GHz 11-bit ADC. A two-chip implementation is presented, using BiCMOS and 65nm CMOS processes, together with the block and system-level measurement results. Readers will benefit from the techniques presented, which are highly competitive, both in terms of cost and RF performance, while drastically reducing power consumption.  ·         Provides system-level analysis of direct RF sampling & digitization receivers, from the antenna to the digital channel selection; ·         Includes analysis of broadband non-linearity, applicable for low-pass and band-pass sampling strategies; Describes system-level design of an application-optimized signal conditioner, including a single-inductance multi-slope programmable RF amplitude equalizer, together with its control algorithm and a mixed-signal AGC loop combining RMS and peak detection.  .

a Topical term or geographic name as entry element Engineering.

a Topical term or geographic name as entry element Microprocessors.

a Topical term or geographic name as entry element Electronic circuits.

a Topical term or geographic name as entry element Circuits and Systems.

a Topical term or geographic name as entry element Signal, Image and Speech Processing.

a Topical term or geographic name as entry element Processor Architectures.

u Uniform Resource Identifier (R) http://dx.doi.org/10.1007/978-3-319-01150-9

c item type EBK

a descripción COM