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Biblioteca Julio Castiñeiras. Sistema de Información Integrado - Facultad de Ingeniería UNLP
Facultad de Ingeniería | 115 esq.47 | Horario: Lunes a Viernes 8 a 19 hs.
E-mail: bibcentral@ing.unlp.edu.ar
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Información bibliografica (registro INGC-EBK-000282) |
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Título: |
Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs by Brandon Noia, Krishnendu Chakrabarty. |
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Autor:
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Noia, Brandon.
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Otros autores: |
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Chakrabarty, Krishnendu.
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Editado por: |
Springer International Publishing :;Imprint: Springer,
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Año de publicación: |
2014.
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Lugar de publicación: |
Cham :
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Descripción física: |
xviii, 245 p. : il. |
ISBN: |
9783319023786
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Materias: |
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Processor Architectures. |
Circuits and Systems. |
Electronic circuits. |
Semiconductors. |
Microprocessors. |
Engineering. |
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Notas: |
Introduction -- Wafer Stacking and 3D Memory Test -- Built-in Self-Test for TSVs -- Pre-Bond TSV Test Through TSV Probing -- Pre-Bond TSV Test Through TSV Probing -- Overcoming the Timing Overhead of Test Architectures on Inter-Die Critical Paths -- Post-Bond Test Wrappers and Emerging Test Standards -- Test-Architecture Optimization and Test Scheduling -- Conclusions. |
Sumario: |
This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.  â_¢Â Provides a comprehensive guide to the challenges and solutions for the testing of TSV-based 3D stacked ICs; â_¢Â Includes in-depth explanation of key test and design-for-test technologies, emerging standards, and test- architecture and test-schedule optimizations; â_¢Â Encompasses all aspects of test as related to 3D ICs, including pre-bond and post-bond test as well as the test optimization and scheduling necessary to ensure that 3D testing remains cost-effective.  . |
URL: |
http://dx.doi.org/10.1007/978-3-319-02378-6
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Tapa y contenido (Amazon.com) |
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